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3D TSV interconnects enter commercialization phase in digital world with Xilinx

Wed, 10/27/2010 - 1:33am
I-Micronews

This is a major step toward the commercialization of 3D TSV interconnects in digital applications based on "2,5D" silicon interposer. Xilinx, Inc. today announced the industry’s first stacked silicon interconnect technology for delivering breakthrough capacity, bandwidth and power savings using multiple FPGA die in a single package for applications that require high-transistor and logic density, as well as tremendous levels of computational and bandwidth performance. By embracing 3D packaging technologies and through-silicon vias (TSV) for its 28nm 7 series FPGAs, Xilinx’s Targeted Design Platforms can address systems with resource requirements that are more than double the reach of the largest single-die FPGAs. This innovative platform approach enables Xilinx to overcome the boundaries of Moore’s Law and offer electronics manufacturers unparalleled power, bandwidth and density optimization for the large-scale-integration of their systems.

“One of the ways the 28nm Xilinx® 7 series FPGAs extend the range of applications programmable logic can address is by offering industry-leading capacity of up to 2 million logic cells. Our stacked silicon interconnect packaging approach makes this remarkable achievement possible,” said Vincent Tong, Xilinx Senior Vice President. “Five years of Xilinx research and development coupled with industry leading technology from TSMC and our assembly suppliers has made possible our efforts to provide an innovative solution for enabling electronic systems developers to take the benefits of FPGAs further into their manufacturing flow.”

With software support available in ISE® Design Suite 13.1,which is currently available to beta customers, the 28nm Virtex-7 LX2000T device will be the world’s first multi-die FPGA and provide more than 3.5X the logic capacity of the largest current-generation Xilinx 40nm FPGA with serial transceivers and 2.8X the logic capacity of the largest competing 28nm FPGA with serial transceivers. The device is made possible by industry-leading micro-bump assembly, advanced technology from TSMC and patented FPGA architectural innovations from Xilinx that deliver lower levels of power consumption, system cost and circuit board complexity compared to using multiple FPGAs, each in their own package, for the same application.

“Compared with traditional monolithic FPGAs, multi-chip packaging approach is an innovative way to deliver large-scale programmability with favorable yield, reliability, thermal gradient, and stress tolerance characteristics,” said Shang-yi Chiang, Senior Vice President of R&D at TSMC. “By using through-silicon via technology and silicon interposer to implement a stacked silicon interconnect approach, Xilinx expects to reduce risks and is on the way to volume production with well-designed test vehicle runs that meet the company’s criteria for design enablement, manufacturability validation, and reliability assessment.”

Within the Xilinx stacked silicon interconnect structure, data flows between a set of adjacent FPGA die across more than 10,000 routing connections. Compared with having to use standard I/O connections to integrate two FPGAs together on a circuit board, stacked silicon interconnect technology provides over 100X the die-to-die connectivity bandwidth per watt, at one-fifth the latency, without consuming any high-speed serial or parallel I/O resources. By having die sit adjacent to each other and interfaced to the ball-grid-array, Xilinx can avoid the thermal flux and design tool flow issues that would be introduced had a purely vertical die-stacking approach been taken. Xilinx’s choice of 28nm HPL (high-performance, low-power) process technology for the base FPGA device provides a comfortable power budget in the package for integrating FPGA die.

Xilinx stacked silicon interconnect technology serves the most demanding FPGA applications at the heart of next generation electronic systems. The technology’s ultra high-bandwidth, low-latency and low-power interconnect allows customers to implement applications applying the same approaches used for large monolithic FPGA devices, using the software’s built-in auto partitioning capabilities for push-button ease-of use, or hierarchical and team-based design techniques for the highest performance and productivity.

“The Virtex-7 2000T FPGA using stacked silicon interconnect technology is a significant step in FPGA evolution and will enable ARM to implement the latest cores and platform solutions within a single FPGA. This will reduce our development effort, reduce power, and improve performance compared to a multi-FPGA approach,” said John Cornish, EVP and general manager, System Design Division, ARM. “We have been a long time user of the Virtex FPGA technology in the ARM Versatile Express SoC prototyping solutions and this will surely extend our strong position.”

“The availability of proven TSV technology along with low-latency interposer structures is being used effectively by Xilinx to expand the capabilities of their FPGA products,” said Dr. Handel H. Jones founder and CEO of IBS, Inc (Los Gatos, CA). “The technologies used by Xilinx have been used in the high-volume manufacturing environment, with the expectation that the quality and reliability of the finished products will be high, where customer risks are very low.”

Aligned with silicon progress is a robust supply chain that is in place with leading foundry and outsourced assembly and test partners, including TSMC. Software support will be available in ISE Design Suite 13.1, which is currently available to beta customers. Initial devices will be available in the 2nd half of 2011

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