Utilizing copper wire interconnect in semiconductor packages offers a number of advantages over gold wire. Copper wire is more electrically and thermally conductive, allowing it to readily replace gold wire without any decrease in electrical or thermal performance. Copper also possesses stronger mechanical properties and is capable of carrying higher currents than the same diameter gold wire, thereby allowing for longer wire lengths and increased manufacturability. These factors are important for enhanced device performance and yield.
“High-performance analog and mixed-signal markets are extremely competitive and require continuous innovation and enhancement of products and services. Using copper wire interconnect capability allows Intersil to provide its customers with performance and manufacturability advantages. Our business is dependent upon reliable fabrication, packaging and testing of our products and we have worked closely with STATS ChipPAC to select and qualify copper wire interconnect for our package offerings. Copper may well be the new gold in semiconductor packaging,” said Sagar Pushpala, Senior Vice President of Worldwide Operations and Technology at Intersil.
Intersil and STATS ChipPAC completed a stringent qualification process with four major wafer foundries across multiple technology nodes. STATS ChipPAC established a Class 1000 cleanroom to ensure the integrity, yield and reliability of the copper material and a robust assembly and test process that has demonstrated best-in-class yields and reliability that is on par with gold wire bond interconnect.
“There are clear performance and cost benefits with the use of copper wire interconnect. Customer demand is steadily ramping up, particularly as customers see the technology mature and the proven range of package types and applications enabled with copper wire interconnect expand. STATS ChipPAC has shipped over 100 million units with copper wire interconnect in a wide range of leaded and laminate packages. We continue to expand our copper wire program to include more advanced packaging such as advanced wafer fab nodes with delicate bond pad structures, fine bond pad pitch, stacked die, die-to-die bonding and ultra low loop height applications,” said Wan Choong Hoe, Executive Vice President and Chief Operating Officer, STATS ChipPAC.
About STATS ChipPAC Ltd.