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Xilinx and Amkor discuss interposer program

Fri, 03/18/2011 - 2:32am
I-Micronews

As we have explained previously [1,2] the “Stacked Silicon Interconnect” platform is the result of Xilinx five-year research program involving supply chain partners, including TSMC who manufactures the CMOS 28nm FPGA slices and the silicon interposer, Ibiden who manufactures the BGA substrate and Amkor who handles assembly.

At the recent IMAPS Device Packaging Conference (IMAPS-DPC) in Ft McDowell AZ, speakers from Xilinx and Amkor gave presentations that shared more information about this program.

At the IMAPS Global Business Council Meeting, held in conjunction with IMAPS-DPC, Suresh Ramalingam of Xilinx discussed their stacked silicon interconnect technology (SSIT).  Rather than try to interconnect smaller devices on a PWB or MCM, which does not offer enough I/O and results in high latency and high power usage, Xilinx SSIT solution is to connect FPGA “slices” on a silicon interposer which offers massive low latency interconnect (10K routing connections between slices with ~ 1ns latency) and low power consumption. They claim this gives them a 1.9X advantage over their nearest competitor.

The Virtex-7 SSIT will reportedly use 28nm FPGA and a 65nm interposer.  The silicon interposers are 100µm thick, and the TSV through vias with diameters of 10µm to 12µm are fully filled with copper. The micro-bumps are Cu-SnAg alloys  at 45µm pitch. The interposer consists of 4 planarized metal layers (3 damascene copper layers and 1 aluminum layer) based on CMOS 65nm technology from TSMC.

 

The FPGA  “slices” are placed close together to reduce latency. In addition, the silicon interposer provides very high routing density, which allows much wider interfaces and bandwidth between adjacent slices than was possible between packaged parts on a PCB. Moreover, since these signals do not need to be driven through long interconnects, the sizes of the I/O buffers can be made considerably smaller, which saves on power consumption and silicon real estate. They also see better stress management of the 28nm FPGA die when mounted on the 65nm Si interposer. The supply chain they put together includes TSMC, Ibiden and Amkor. Amkor received the FPGA wafers and bumps them. The interposer wafer arrives from TSMC bumped and Amkor does the chip to interposer and interposer to BGA assembly.

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