As with the portable consumer electronics sector, hearing aid design is subject to pressures to enhance operational performance, add new functionality, and extend battery life, while simultaneously retaining compact form factors. This constant conflict of interests makes the development of hearing aids an extremely complex and challenging affair. The following article details the key issues that manufacturers of digital signal processors (DSP) used in hearing aids must address in order to meet the high expectations of end-users.
Overall System Challenges
The digital IC technology incorporated into hearing aids allows amplification and manipulation of sound. ICs may also be involved in providing other features, including wireless communication or management of rechargeable batteries for more sophisticated models. Though some simple system designs only need a single DSP and a memory IC, others require six or seven ICs (including a wireless controller, analog front end, power regulator, etc.) plus discrete components (e.g. Capacitors, circuit protection devices), in order to support more features.
It is necessary for this circuitry to achieve strong performance with relation to both the sound quality it delivers and its computational capability. Given the small battery size and the required battery life time the design must minimize power consumption. Furthermore, the physical size has to be considered. Often trade-offs will be made between the functionality that is included in the hardware platform and the space it will take up.
Hearing aid engineers have a variety of options selecting which DSP architecture should form the basis of their hardware platform. At one end of the spectrum there is the general-purpose open-programmable architectural option. This type of architecture allows the signal processing algorithms to be modified or updated. It accommodates a broad range of signal processing possibilities so that design flexibility is maximized. This flexibility comes at a price however, with a potentially larger die size and greater power consumption ensuing. Given the low-power and small size requirements of modern hearing aids, a general-purpose open-programmable architecture is not ideally suited.
At the opposite end of the spectrum is the closed platform architecture (often referred to as fixed-function) where the signal processing is hardwired into the semiconductor fabric. This option meets both power budget and board size requirements, but does not provide adequate design flexibility. Here, though some parameters can be adjusted, the basic function of the IC cannot be changed without a costly and time-consuming redesign work. Between the two extremes, there are semi-programmable architectures, which attempt to overcome the inherent disadvantages of closed platforms by enabling a certain degree of programmability. In this architecture, main signal processing capabilities are hardwired in logic blocks, but a programmable DSP element enables additional capabilities to be implemented in software without needing to re-spin the chip design. However, if significant changes must be undertaken to the hardwired blocks, or the programmable processor cannot cope with a usual algorithm concept, then a new chip will be necessary. While gaining in flexibility, the use of semi-programmable DSPs risks compromising power efficiency.
Another architectural approach is to implement an application-specific, open-programmable platform. This is designed and optimized for the signal processing needs of a very specific application (e.g. digital audio processing for hearing instruments), while presenting the software flexibility of a general-purpose architecture. Though such architectures are not as power efficient as closed ones, this effect can be minimized through well thought out chip design and a good choice of process geometry.
Power consumption, die size, and system performance are all influenced by the process node utilized. Demand for smaller, faster, cheaper and more reliable ICs with lower power consumption has driven the development of more intricate semiconductor geometries. Increasingly sophisticated hearing aid signal processing algorithms are also driving the need for greater computational resources. Migration to smaller process geometries can satisfy this, as well as helping address the rigid power consumption and size limitations that characterize this type of application.
There are, however, several catches that engineers need to be aware of. Firstly, design and manufacturing complexity increases dramatically at smaller process nodes. There are layout-dependent implications and strict design rules that must be adhered to and the number of rules increases as nodes get smaller. Secondly the financial investment necessary for design, verification, layout, mask sets, and design tools must be factored in. These rise substantially at the smallest process nodes making the latest semiconductor geometries only practical for applications with extremely high unit volumes.
It is critical that careful consideration is given to which functional components should be integrated onto the same semiconductor die. Flexibility is a key factor when making design partitioning decisions. If functional blocks are integrated onto a single die, then the ability to change any of these blocks independently is lost and, should modifications be necessary, the entire chip will have to be revised. This can potentially be both time consuming and expensive.
Adopting Standard Processors in Multi-Core Architectures
Challenged to boost performance and reduce power, many engineers are turning to hearing aid platforms based on multiple processor cores. Multiple cores mean that different computational units can carry out multiple instructions simultaneously, thereby increasing the overall speed. Through the increased computational capacity derived, it is possible to support more advanced algorithms based on new audiology concepts. It also facilitates the introduction of wireless functionality into the platform for data transfer between hearing aids, remote control, and connectivity with other electronic devices. It is a commonly-held misconception that standard processor cores are too inefficient for use in hearing aids. This is primarily due to the stringent power-dissipation requirements and has led to custom-designed cores being employed almost exclusively. While proprietary cores have size and power efficiency advantages, these are becoming less significant as the industry moves to deeper sub-micron technologies. Standard cores offering programmable flexibility have evolved to a point where they can be used in conjunction with specialized cores for certain processing tasks, such as running proprietary wireless baseband functionality to optimize power consumption.
Analog wireless technologies, in the form of telecoil or FM systems, have been used in hearing aids for decades. More recently, near-field magnetic induction (NFMI) and radio frequency (RF) technologies have been introduced. NFMI allows data exchange from one ear to the other for binaural processing. This can enhance voice intelligibility and helps users determine where a sound is coming from. The effective range of NFMI is less than 1 m, so hearing aids founded on this technology must also use an intermediary relay device (normally worn around the user’s neck) to communicate across greater distances. Typically, Bluetooth technology would be utilized for the communication link between a relay device and a Bluetooth-compatible audio source.
Recent hearing instruments encompass RF technology and allow data transmission with ranges up to 9 m, eliminating the need for relay devices.
As we have seen, there are many areas of concern for hearing aid designers when they are looking to implement an effective hardware platform in a market that is dynamic and continuously progressing in technology. With new trends appearing and an underlying atmosphere of uncertainty always present, design flexibility is crucial - chip vendors must therefore offer applicable products. In response to this, ON Semiconductor has created the Ezairo 7100. This is a highly- integrated system-on-chip solution featuring a quad-core, 24-bit, open-programmable DSP, which allows manufacturers the provision to develop their own unique algorithms. With a power consumption < 0.7 mA, it supports clock speeds of 10.24 MHz and clock throttling extends its computational capacity. The integrated wireless controller (which is NFMI and RF compatible) supports efficient data transfer.