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Last week, in a presentation made at Semicon Taiwan, senior engineering and R&D manager Kauppi Kujala of Nokia disclosed the company roadmaps for 3D integration. He described the steps from “2.5D” to true “3D” using various applications of TSVs in silicon interposers, memories and integrated circuits (ICs).

He focused particularly on the “wide IO interface” concept, which aims at increasing the bandwidth between the memory and its driving logic IC thanks to a large “high IO count” data bus between the two circuits. M. Kujala announced that Nokia is planning to integrate wide IO interface structures using TSVs for mobile phones in volumes starting in 2013. These integrated solutions will first be driven in high end phones addressing the need for higher bandwidth between the application processor and its DRAMs and for lower power consumption too. Nokia’s preference and first target is to integrate a stack of 4 DRAMs with TSVs on a processor with TSVs, all in a single package.

 

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