Several themes emerged from this meeting including: (1) while everyone has bought into the inevitability of 3D IC the lack of standardization seems to be gating adoption of the technology; ( 2) everyone’s roadmaps now look remarkably alike which either means that we are reaching consensus on timing or that they are being made to intentionally all look alike so no one looks like they are behind; (3) there also appears to be general buy-in on “2.5D” (the 3D interposer) since it will be used to “bridge the gap” to 3D IC and because it will be needed in order to package 32 and 22 node CMOS chips in the near future; (4) the big driver application looks like it is wide I/O memory and logic; (5) there still is not a clear division of labor between the foundries and the assembly houses; and lastly (6) now that manufacturers are looking at HVM process details technical issues are becoming more apparent (although most of them look like engineering issues that simply need to be worked through).
Chien predicts that DRAM stacking will be seen in the 2009 – 2011 timeframe, logic + wide I/O DRAM stacking will occur in 2011-2012 and heterogeneous stacking like Rf + DRAM +ASIC will be seen sometime following that.
UMC proposes that silicon interposers ( 2.5 D) will evolve into two categories depending on whether packaging RDL technology or Dual Damascene IC technology are used to create them as shown in the table below.
UMC reveals that they are finding vias middle scaleup problems such as Cu TSV extrusion, Cu voiding, oxide liner cracking and interface ILD cracking which have led them to take anther look at vias last (from the backside).
UMC outlined a division of labor with their 3D IC partners Elpida and PTI as follows.
ITRI sums up all the challenges for 3D IC manufacturing as all relating to thin wafer handling. Thin wafers must be managed during temporary bonding, back grinding, metallization, - chemical processes, debonding, dicing etc.
ITRI offers the following summary of some of the high profile temporary bonding solutions :
Their roadmap shows single chip logic on interposer use in late 2010, memory stacking and logic and memory on interposer in 2011 and heterogeneous stacking post 2012. Chen commented that their 3D technology will “turn on in the very near future, depending on some technological breakthroughs and cost level”
SPIL copper pillar joining technology is detailed in the figure below.
Qualcomm suggests the following Standards and proposes that the following standards bodies be involved because “standards will accelerate adoption of the technology”:
Kujala sees interposers being driven by technical limitations such as “…die vs substrate pitch miss match and low K mechanical issues. In addition interposers can be complemented with IPDs (integrated passive devices)” In the end Kujala sees that “cost will be the critical item”.
When it comes to memory stacking, Kauppi Kujala, Sr Tecnology Mgr at Nokia reports that TSV can offer “..clear miniaturization opportunities (and) also performance and power reduction”
Like many others in the field, Nokia agrees that the main driver will probably be wide I/O memory mating with memory starved logic devices. Nokia preference and first target for Wide IO package is a single package with 4 DRAM with “.. High end smart phones are initially driving the development. Migration to mid segment and lower categories will follow later”
Vs PoP, wide I/O memory stacking with TSV is expected to deliver 35% package size reduction, 50% power consumption reduction and 8X the bandwidth.
Kujala, in agreement with Lu from Qualcomm sees the need for standardization commenting that “Standardization of interface between chips is a must for real mix and match of different chips from different suppliers” Nokia is active on the JEDEC wide I/O standardization committee which should have standards ready in late 2011.