Attendees will benefit by gaining the latest knowledge with eight application-oriented tutorials, 10 technical sessions, two expert panel discussions, and a keynote presentation from distinguished speaker Raj Master, General Manager, Microsoft Hardware Silicon, Packaging, Quality and Reliability, titled "Thermal and Power Considerations in Electronics Packaging."
The conference includes three tracks with two days of technical paper presentations covering: Wafer Level Packaging; 3-D (Stacked) Packaging; and MEMS Packaging.
Exhibit space is limited but there are still tabletop spaces available. Please contact Seana Wall, firstname.lastname@example.org, at SMTA or any sales representative with Chip Scale Review at email@example.com with questions or for more information about the exhibition.
This premier industry event explores leading-edge design, material, and process technologies focused on Wafer-Level Packaging applications. There will be special emphasis on the numerous device and end product applications (RF/wireless, sensors, mixed technology, optoelectronics) that demand wafer-level packaging solutions for integration, cost, and performance requirements.
Visit http://www.iwlpc.com for more information.