The latest signal chain components available for medical imaging systems enable designers to improve signal chain density and power consumption without compromising dynamic performance. Additionally, these technologies allow systems to improve their image quality, power consumption, and size. This article reviews these exciting products.
By Chuck Sanna
Chuck Sanna is a product marketing engineer with high-speed analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) at Texas Instruments. He earned a BS in electrical engineering from Northwestern University and an MS in electrical engineering at the University of Texas at Dallas. Sanna can be reached at email@example.com .
Concurrently, manufacturers are driven to improve their system’s size, power consumption, and performance. Enhancing performance in one area can cause challenges in others. Simply adding sensors and signal chains can cause both system size and power consumption to increase. But, the newest generation of signal chain components available to medical imaging systems enables designers to improve signal chain density and power consumption without compromising dynamic performance—simultaneously allowing systems to improve their image quality, power consumption, and size.
Medical Imaging Receiver ElementsFor most typical medical imaging applications, each sensor array element requires its own signal chain to convey and convert the sensor’s small signal responses into one matched for digital signal processing. Because signal responses vary for sensors used in imaging applications, usually there are multiple active elements involved in the signal’s conversion process. Typically, the first is a low-noise amplifier (LNA), the primary purpose of which is to fix the analog system’s noise figure as low as possible. A second amplifier usually follows the LNA to optimally match the signal to the input swing of the final stage—the analog-to-digital converter (ADC).
Integration: More Chains, Less Space, Lower PowerIntegrating ever increasing numbers of analog devices onto a single chip, while reducing the total number of ICs required in a system, is a major innovation. Consider a typical ultrasound receive chain. Potentially, there are four devices per sensor, three of which are amplifiers. With modern design and processing, IC suppliers now offer devices that combine the LNA, VGA, and PGA into a single variable gain amplifier—cutting the number of chips by one-third over a discrete solution. Many designs go a step further by integrating multiple VGA channels into one IC. Eight VGA channels are included in a single IC packaged in a 64-pin QFN package. The device goes one step further by integrating a low-pass, anti-aliasing filter after the PGA. This allows the VGA output to go directly into an ADC’s input without external passive or active components, saving even more board space. In Figure 1, other functional blocks particular to medical imaging systems, such as a continuous wave switch matrix and clamping circuit, are also integrated into this device.
Integrating multiple channels into one device has other benefits beyond size. Typically, each component is designed to achieve a balance of power and performance as a standalone entity. Although designed to work together, each component is likely to perform better than required for the system. Consequently, when working together, each tends to skew the power versus performance balance towards over-performance with higher than desired power consumption.
But in multi-stage ICs, designers can allocate power to most efficiently meet design requirements, wasting little power on blocks that don’t need it. Newer VGAs are good examples. Because low noise is critical to ultrasound imaging systems, the LNA function is critical to the VGA design. Its input noise sets the minimum achievable noise figure for the system, while its gain also directly affects the amount of noise from subsequent stages impacting the final noise figure. By balancing power versus performance in the LNA stages, lower power designs can be achieved while improving the VGA’s performance (Figure 2). Previous multi-channel VGAs lay upon a trend line, trading off power and input referred noise. A design could be used that only consumed 75 mW per channel to acheive 1.2 nV/?Hz input referred noise; or have 0.7 nV/?Hz input referred noises, if 150 mW per channel power consumption doesn’t overload the power budget. But owing to very efficient low-noise bipolar junction transistors (BJTs), today’s VGAs can optimize front end design so that 0.8 nV/?Hz input referred noise can be achieved for only 63 mW per channel. This allows high-performance imaging systems to draw less power while becoming smaller and more portable.
Squeezing the Power
ADC power consumption has been dramatically reduced without affecting performance in the typical medical imaging application’s operational envelope. Because of the noise and linearity requirements imposed by imaging applications, efficient amplifier stages are usually built-in processes such as silicon germanium to utilize low-noise BJTs. These processes offer an outstanding balance of low noise, low power, and high linearity for typical response frequencies from DC to 20 MHz. Conversely, high-speed ADCs with the typical sampling rates needed for medical imaging are generally built using a CMOS process as it offers a good balance between power and performance for 10- to 14-bit resolution converters up to and beyond 65 MSPS.
With advancements in CMOS technology, the ADCs power consumption and footprint have been significantly reduced without affecting their noise and distortion performance, as proven with the ADS5281. This ADC reduces power by nearly 50% and footprint by almost 60% over a previous generation octal design, all while maintaining 70 dB SNR.
CMOS-based ADCs facilitate designs that offer additional power savings and dynamically scale their power consumption with sample rate. As the sample rate is lowered, less power is demanded by the ADC core and data output blocks. Newer power-efficient ADCs take advantage of this to scale their power dissipation, depending on the sampling clock input to the IC. Figure 3 shows how the ADS5281/82 scales over sample rate. At the high-end (65 MSPS), the ADC consumes 77 mW per channel, but at a lower speed (20 MSPS), it only consumes 43 mW, or 45% less power. ADCs can switch into a power-saving mode, yet still be able to convert limited analog signals and pass them to the digital processing engine.
Increased ADC performance, with respect to input frequency (IF), have made completely new system architectures in MRI possible. The MRI machine’s main magnets produce a narrow-band IF ranging from 30 to 140 MHz, depending on the main magnetic field’s strength. Traditional architecture mixes the IF down to near DC where it can be sampled by a precision delta-sigma ADC. Now, newer 14- and 16-bit ADCs can easily sample IFs in this range while maintaining high performance, even when under sampling. With digital decimation and down conversion, these ADCs can achieve similar SNR to that achieved by using traditional architectures, saving board space and cost of analog mixing elements, while improving imaging performance.