The ADP5041 has a special circuit that detects a three-state condition when applied to the watchdog refresh input at the WDI pin typically controlled by a processor/DSP output port. When the processor sets this port in three-state mode, the watchdog refresh timer is disabled, preventing a watchdog reset to the processor. This feature is important when supporting processor/DSP sleep operation where the core is disabled and watchdog timer cannot be refreshed.
The ADP5040 and ADP5041 multi-output regulators reduce thermal dissipation by using high-efficiency switching regulators with up 96 percent buck power efficiency. For low-noise analog circuit applications, the LDOs maintain a power supply rejection greater than 60 dB for frequencies as high as 10 kHz while operating with a low headroom voltage. The ADP5041 and ADP5040 also provide a three-rail system power supply (1.2-A buck regulator and two 300-mA LDOs) with adjustable output voltages, which allows output voltages to be easily set using an external resistor divider network. The 3-MHz buck regulator switching frequency allows small ceramic inductors to be used to further reduce solution size and cost. These features allow the ADP5041 and ADP5040 to be easily and quickly modified for a variety of applications with short product design schedules such as portable medical and industrial devices.
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